Array processor

Design under verification(DUV) is reconfigurable array processor which has 32 ALUs in a unit. Verification environment is well constructed based on VMM using constrained random verification and coverage based verification.
Special features in this verification environment are:
to generate max 72M instructions, to generate internal bus traffic,
to realize error injection by CRV
automatic data checking by scoreboard,
to realize incremental verification environment and
to make proprietary debug environment with effective messages.

Interconnect

Design under verification(DUV) is interconnect in SoC to which over 20 IPs including multiple CPUs are connected. Verification environment generates bus traffic close to actual application environment to verify several blocks including bridges, arbiters and memory controller.

Reduce simulation time by grid engine

We always face on problems that it takes some amount of time for simulation. We have constructed grid environment using 3 SUN workstations to improve this situation. We have succeeded in reducing simulation time from 17 hours to only 30 minutes under this environment.

■Grid verification environment

■Simulation time under grid computing

Examples