In recent years timing controllers have become more complicated by a variety of factors such as blocks for timing adjustment, scalability and image-processing blocks for presenting the panel’s feature. In performing verification of high-definition digital TV / displays including 4K TVs, which require enormous amount of data, it is essential to carefully choose the timing, goals and methods of simulation, emulation and FPGA prototyping in the verification process. We develop the most efficient verification plans, propose / develop verification IP of image I/O, and design / verify image processing blocks.